1. Field
Exemplary embodiments of the present invention relate to a memory device, and more particularly, to a refresh technology of a memory device.
2. Description of the Related Art
A memory cell of a memory device may include a transistor serving as a switch and a capacitor storing charges (data). A ‘high’ (logic 1) and a ‘low’ (logic 0) of the data are divided according to whether there is no charge in the capacitor within the memory cell, that is, according to whether a terminal voltage of the capacitor is high or low.
The data are stored in a form in which the charge is accumulated in the capacitor and therefore, in principle, there is no power consumption. However, an initial charge amount stored in the capacitor may be extinguished due to leakage current caused by a PN junction of an MOS transistor and therefore, data may be lost. In order to prevent data from being lost, there is a need to read the data within the memory cell before the data are lost and recharge the normal charge amount again according to the read information. The storage of the data is maintained by periodically repeating the operation. The recharging process of the cell charge is referred to as a refresh operation.
The refresh operation is sorted into an auto refresh operation performed when a refresh command is applied from a memory controller to a memory device and a self refresh operation performed by a memory itself when the memory controller sets the refresh period. Meanwhile, the current auto refresh operation is defined as refreshing each row in all the banks in the memory device, respectively, when the memory controller applies the refresh command to the memory device. However, all the banks are simultaneously refreshed at the time of the auto refresh operation and therefore, peak current consumption of the memory device is increased such that power shortage, noise increase, and the like, may occur. Therefore, a need exists for a technology of resolving the concerns.